1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
FIG. 1 illustrates bitline bouncing on a semiconductor memory device.
According to FIG. 1, the semiconductor memory device reads data by the following method: a row address is entered into a circuit and data of a memory cell corresponding to the row address is amplified by a bitline sense amplifier. Then, a bitline pair (BL, BLB) and an input/output line pair (LIO, LIOB) corresponding to a column address are connected, and an input/output sense amplifier then reads the memory cell data. Here, the bitline pair (BL, BLB) and the input/output line pair (LIO, LIOB) are connected by a switching transistor formed between the bitline pair (BL, BLB) and the input/output line pair (LIO, LIOB), which is enabled, by responding to a column selection line signal provided with the decoded column address.
A current type input/output sense amplifier supplies an electric current, and senses any change in the current amount, and reads the memory cell data. The electric current flows into the bitline pair (BL, BLB) via the switching transistor, and one of the bitline pair with a low level, i.e. the bitline bar (BLB), rises to a reference level by the flowed electric current, as denoted by “a” in FIG. 1. However, the other one of the bitline pair with a high level, i.e. the bitline (BL), drops to a reference level, as denoted by “b” in FIG. 1. This rise and drop is referred to as “bitline bouncing”. As illustrated in a′ and b′ in FIG. 1, as the magnitudes of the bitline pair voltages increase, the possibilities of reversing the bitline pair logic levels correspondingly increase. Accordingly, the possibilities of failure increase.
As the semiconductor memory device is highly integrated, a pitch between the bitline pair (BL, BLB) gets closer. As a result, there is not enough space to form the bitline sense amplifier in between the bitline pair (BL, BLB), resulting in a decrease in the number of contacts. In other words, the bouncing voltage rises as the bitline sense amplifier resistance rises.
An internal array source voltage (VINTA) is used in the bitline sense amplifier. As the internal array source voltage (VINTA) level decreases, a potential difference between the bitline pair also decreases when the data stored in a capacitor in the memory cell develops. Therefore, the bitline bouncing may result in higher possibilities of reversing the bitline pair logic levels.